Fix FPU problem and add basic RISC-V64 support

[saicogn]

PR checklist

• Updated function header with a short description and version number
• Added test case for bug fix or new feature
• Validated on real hardware

[yf13]

@salcogn, can you teach what RiscV chip is targeted by this patch?

[saicogn]

@salcogn, can you teach what RiscV chip is targeted by this patch?

The CV1800B RISC-V64 chip contains two T-Head C906 processors, and ThreadX runs on the small C906 core without MMU.

[yf13]

@alcogn, thanks! that sounds like a milkv duo device. I am wondering if targeting qemu-system-riscv64 can be easier for sharing?

[saicogn]

@alcogn, thanks! that sounds like a milkv duo device. I am wondering if targeting qemu-system-riscv64 can be easier for sharing?

Yes，target device is Milk-duo 64MB. Here is a detailed repo. And you are right, targeting qemu-system-riscv64 is easier to share, I am also working on relevant adaptation work.