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ModelNetlist
ModelNetlist PublicThis repository contains a simple model for representing netlist (electronics) in python
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open-rtl-competition
open-rtl-competition PublicThis repository contains an open rtl (register-transfer-level) competition that is hosted by chiphackers.com
Perl 2
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DesignExamples
DesignExamples PublicThis repository contains the design examples mentioned in https://chiphackers.com/lessons/
Verilog 1
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- ModelNetlist Public
This repository contains a simple model for representing netlist (electronics) in python
chiphackers/ModelNetlist’s past year of commit activity - DesignExamples Public
This repository contains the design examples mentioned in https://chiphackers.com/lessons/
chiphackers/DesignExamples’s past year of commit activity - zscore-wiki Public
This repository contains the user guide and issue tracker for zscore.lk exam prep platform
chiphackers/zscore-wiki’s past year of commit activity - covered Public
Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
chiphackers/covered’s past year of commit activity - open-rtl-competition Public
This repository contains an open rtl (register-transfer-level) competition that is hosted by chiphackers.com
chiphackers/open-rtl-competition’s past year of commit activity
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