Fix serial I/O missing beta for bubbles_lagrange in post_process

[sbryngelson]

Summary

With parallel_io=F (serial/no-MPI builds), post_process aborts with q_cons_vf8.dat is missing for any bubbles_lagrange=T case. This is a regression that only affects serial builds — parallel builds (parallel_io=T) work correctly.

Root cause: Two issues in the serial I/O path:

1. s_write_serial_data_files did not write the Lagrangian void fraction (beta) to p_all/ as q_cons_vf(sys_size+1).dat, while s_write_parallel_data_files correctly does so via alt_sys = sys_size + 1. Meanwhile, post_process always includes beta_idx in sys_size when bubbles_lagrange=T, so it always expects this file.

2. t_step_start output is written by pre_process, which has no knowledge of Lagrangian beta. So even with fix Error on READE.md #1, t_step_start = 0 would still be missing the beta file.

Changes

• src/simulation/m_data_output.fpp: write beta as q_cons_vf(sys_size+1).dat in s_write_serial_data_files, mirroring the parallel I/O path.
• src/post_process/m_data_input.f90: when bubbles_lagrange=T and i == beta_idx and the file is absent, initialize beta to zero instead of aborting. This handles the t_step_start timestep written by pre_process.

Test plan

• Run a bubbles_lagrange=T case with parallel_io=F through all stages (pre_process → simulation → post_process) and confirm no abort
• Confirm existing parallel_io=T Lagrangian cases are unaffected
• Confirm non-Lagrangian cases are unaffected (error path still triggers for truly missing files)

🤖 Generated with Claude Code

[codecov]

Codecov Report

❌ Patch coverage is 42.85714% with 4 lines in your changes missing coverage. Please review.
✅ Project coverage is 44.04%. Comparing base (1412eb2) to head (9892f43).
⚠️ Report is 4 commits behind head on master.

Files with missing lines	Patch %	Lines
src/post_process/m_data_input.f90	0.00%	2 Missing ⚠️
src/simulation/m_data_output.fpp	60.00%	1 Missing and 1 partial ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##           master    #1274      +/-   ##
==========================================
- Coverage   44.05%   44.04%   -0.02%     
==========================================
  Files          70       70              
  Lines       20496    20499       +3     
  Branches     1991     1993       +2     
==========================================
- Hits         9029     9028       -1     
- Misses      10328    10330       +2     
- Partials     1139     1141       +2     

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[github-actions]

Claude Code Review

Head SHA: 9892f43

Files changed: 2

• src/simulation/m_data_output.fpp (+13 / -0)
• src/post_process/m_data_input.f90 (+4 / -0)

---

Summary

• Fixes a serial I/O regression (parallel_io=F) where post_process aborts with q_cons_vf<N>.dat is missing for bubbles_lagrange=T cases.
• s_write_serial_data_files now writes beta as q_cons_vf(sys_size+1).dat, mirroring the existing parallel I/O path.
• s_read_serial_data_files now zero-initializes beta instead of aborting when the file is missing and bubbles_lagrange=T.
• Changes are additive (no deletions); existing serial/parallel paths for non-Lagrangian cases are untouched.

---

Findings

1. Over-broad silent zero-initialization guard — moderate concern

File: src/post_process/m_data_input.f90, added else if block (line ~315)

The new guard triggers for any timestep where the beta file is absent when bubbles_lagrange=T and i == beta_idx, not only at t_step_start. The PR description correctly identifies that the missing-file scenario only legitimately occurs at t_step_start (written by pre_process before simulation has produced Lagrangian beta). For all other timesteps a missing beta file indicates a real I/O error, but the current code would silently zero-initialize rather than abort, masking data corruption.

Suggested fix — tighten the guard:

else if (bubbles_lagrange .and. i == beta_idx .and. t_step == t_step_start) then
    ! beta not written by pre_process; initialize to zero for t_step_start only.
    q_cons_vf(i)%sf(0:m, 0:n, 0:p) = 0._wp

This preserves the abort path for any non-initial timestep where the file is unexpectedly missing.

2. Implicit beta_idx == sys_size + 1 coupling — low concern

File: src/simulation/m_data_output.fpp and src/post_process/m_data_input.f90

The simulation writes at index sys_size + 1; the post_process reads at beta_idx. Correctness depends on beta_idx == sys_size + 1 always holding when bubbles_lagrange=T. This appears to be true given the global parameter setup, but the coupling is implicit. A comment in m_data_output.fpp asserting this relationship (or a compile-time @:ASSERT(beta_idx == sys_size + 1, ...) at the read site) would make the invariant explicit and prevent future regressions if the index layout changes.

3. STATUS='new' — no action needed

Consistent with the surrounding loop for other q_cons_vf files. Correct for the write path.

---

No other issues found

The fix is minimal, targeted, and correctly mirrors the parallel I/O path. Addressing finding #1 (tightening the zero-init guard to t_step_start only) is the main recommended change before merge.

[coderabbitai]

Caution

Review failed

The pull request is closed.

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📥 Commits

Reviewing files that changed from the base of the PR and between 33ab04e and 9892f43.

📒 Files selected for processing (2)

• src/post_process/m_data_input.f90
• src/simulation/m_data_output.fpp

---

📝 Walkthrough

Walkthrough

Two files are modified to support Lagrangian bubble void fraction data handling. In m_data_output.fpp, a new code block writes beta data to an additional file (q_cons_vf(sys_size+1).dat) when the bubbles_lagrange flag is enabled, using the same unformatted write pattern as existing q_cons_vf files. In m_data_input.f90, the serial data reading function adds a fallback that initializes the beta index to zero instead of aborting when the file is missing, but only if bubbles_lagrange is true. Together, these changes establish an I/O pathway for Lagrangian beta data between output and input stages.

---

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[Copilot]

Pull request overview

Fixes a regression in serial (non-MPI) post_process for bubbles_lagrange=T cases by ensuring the Lagrangian void fraction (beta) is available to read, matching the parallel I/O expectations.

Changes:

• Update simulation serial output to write beta as q_cons_vf(sys_size+1).dat, aligning with the parallel I/O numbering scheme.
• Update post_process serial input to avoid aborting when the beta file is missing (intended to cover t_step_start written by pre_process) by initializing beta to zero.

Reviewed changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 2 comments.

File	Description
src/simulation/m_data_output.fpp	Adds serial unformatted output of Lagrangian beta as an extra q_cons_vf(sys_size+1) file.
src/post_process/m_data_input.f90	Adds a missing-file fallback for beta_idx during serial reads to prevent abort on the pre_process-written first timestep.

[Copilot]

beta is an OPTIONAL dummy argument, but this block dereferences beta%sf guarded only by bubbles_lagrange. If s_write_serial_data_files is called without the optional beta actual argument (even if bubbles_lagrange is true due to input/state), this will be an invalid reference at runtime. Guard the write with present(beta) (and optionally also bubbles_lagrange) to match the parallel I/O path’s logic.

[Copilot]

This fallback initializes beta to zero whenever the beta file is missing, for any t_step. That can silently hide real I/O/data corruption for later steps (and yield incorrect post-processed results). Consider restricting the zero-initialization to the known pre_process-only step (e.g., t_step == t_step_start / the first step being processed), and keep aborting for missing beta files at other timesteps (or at least emit a clear warning).

Suggested change

	else if (bubbles_lagrange .and. i == beta_idx) then
	! beta (Lagrangian void fraction) is not written by pre_process
	! for t_step_start; initialize to zero.
	else if (bubbles_lagrange .and. i == beta_idx .and. t_step == t_step_start) then
	! beta (Lagrangian void fraction) is not written by pre_process
	! for t_step_start; initialize to zero only on that timestep.